View IRFB4110PBF_312611.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PD - 97061A
IRFB4110PBF
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits
HEXFET(R) Power MOSFET
VDSS RDS(on) typ. max ID
D
100V 3.7m: 4.5m: 180A
D
Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability
G
G D
S
S
TO-220AB
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current d Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery f Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw Single Pulse Avalanche Energy e Avalanche Current c Repetitive Avalanche Energy g
Max.
180c 130c 670 370 2.5 20 5.3 -55 to + 175 300 10lbxin (1.1Nxm) 210 75 37
Units
A
W W/C V V/ns C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA
Parameter
Junction-to-Case k Case-to-Sink, Flat Greased Surface Junction-to-Ambient j
Typ.
--- 0.50 ---
Max.
0.402 --- 62
Units
C/W
www.irf.com
1
11/3/05
IRFB4110PBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage
Min. Typ. Max. Units
100 --- --- --- 0.108 --- --- 3.7 4.5 2.0 --- 4.0 --- --- 20 --- --- 250 --- --- 100 --- --- -100
Conditions
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAd m VGS = 10V, ID = 75A g V VDS = VGS, ID = 250A A VDS = 100V, VGS = 0V VDS = 100V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd RG td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
160 --- --- ---
---
Conditions
VDS = 50V, ID = 75A ID = 75A VDS = 50V VGS = 10V g VDD = 65V ID = 75A RG = 2.6 VGS = 10V g VGS = 0V VDS = 50V = 1.0MHz VGS = 0V, VDS = 0V to 80V j VGS = 0V, VDS = 0V to 80V h
--- 150 35 43 1.3 25 67 78 88 9620 670 250 820 950
--- 210 --- --- --- --- --- --- --- --- --- --- --- ---
S nC
--- --- --- --- --- --- --- Effective Output Capacitance (Energy Related)i --- --- Effective Output Capacitance (Time Related)h
ns
pF
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) di Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- 170c --- 670 A
Conditions
MOSFET symbol showing the integral reverse
G D
S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 75A, VGS = 0V g VR = 85V, --- 50 75 ns TJ = 25C TJ = 125C IF = 75A --- 60 90 di/dt = 100A/s g --- 94 140 nC TJ = 25C TJ = 125C --- 140 210 --- 3.5 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes: Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.074mH RG = 25, IAS = 75A, VGS =10V. Part not recommended for use above this value. ISD 75A, di/dt 630A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom R is measured at TJ approximately 90C.
Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994.
2
www.irf.com
IRFB4110PBF
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
ID, Drain-to-Source Current (A)
BOTTOM
ID, Drain-to-Source Current (A)
BOTTOM
4.5V
100
4.5V
100
60s PULSE WIDTH
Tj = 25C 10 0.1 1 10 100 V DS, Drain-to-Source Voltage (V)
60s PULSE WIDTH
Tj = 175C 10 0.1 1 10 100 V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
RDS(on) , Drain-to-Source On Resistance (Normalized)
Fig 2. Typical Output Characteristics
3.0 ID = 75A 2.5 VGS = 10V
ID, Drain-to-Source Current (A)
100
2.0
10 T J = 175C 1
T J = 25C
1.5
1.0
VDS = 25V 60s PULSE WIDTH 0.1 1 2 3 4 5 6 7
0.5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds SHORTED Crss = C gd Coss = Cds + Cgd
Fig 4. Normalized On-Resistance vs. Temperature
12.0 ID= 75A
VGS, Gate-to-Source Voltage (V)
10.0 8.0 6.0 4.0 2.0 0.0
C, Capacitance (pF)
10000
Ciss
VDS= 80V VDS= 50V
Coss 1000 Crss
100 1 10 VDS, Drain-to-Source Voltage (V) 100
0
50
100
150
200
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
www.irf.com
3
IRFB4110PBF
1000 10000 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000
100sec
100
T J = 175C
10
T J = 25C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
10msec
1 VGS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 VSD, Source-to-Drain Voltage (V)
10 Tc = 25C Tj = 175C Single Pulse 1 0 1
DC
1msec
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig 8. Maximum Safe Operating Area
125 Id = 5mA 120 115 110 105 100 95 90 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C )
180 160 140
ID, Drain Current (A)
Limited By Package
120 100 80 60 40 20 0 25 50 75 100 125 150 175 T C , Case Temperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
5.0 4.5 4.0 3.5
Energy (J)
EAS , Single Pulse Avalanche Energy (mJ)
Fig 10. Drain-to-Source Breakdown Voltage
900 800 700 600 500 400 300 200 100 0 ID 17A 26A BOTTOM 75A TOP
3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 20 40 60 80 100 120
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (C)
4
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
www.irf.com
IRFB4110PBF
1 D = 0.50 0.1 0.20 0.10 0.05 0.01 0.02 0.01
J R1 R1 J 1 2 R2 R2 R3 R3 C 1 2 3 3 C
Thermal Response ( Z thJC )
0.001
C i= i/R i C i= i/Ri
Ri (C/W) 0.09876251 0.2066697 0.09510464
i (sec) 0.000111 0.001743 0.012269
SINGLE PULSE ( THERMAL RESPONSE )
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1
0.0001 1E-006
1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
0.01 0.05
10
Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses
0.10
1
0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
250 TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 75A
EAR , Avalanche Energy (mJ)
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
175
0 25 50 75 100 125 150 Starting T J , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
www.irf.com
5
IRFB4110PBF
4.0
VGS(th) , Gate threshold Voltage (V)
25 IF = 30A V R = 85V TJ = 25C TJ = 125C
3.5 3.0
20
2.0 1.5 1.0 0.5
ID = 250A ID = 1.0A
IRR (A)
2.5 ID = 1.0mA
15
10
5
0
-75 -50 -25 0 25 50 75 100 125 150 175 200
0
200
400
600
800
1000
T J , Temperature ( C )
diF /dt (A/s)
Fig 16. Threshold Voltage vs. Temperature
25 IF = 45A V R = 85V TJ = 25C TJ = 125C
QRR (A)
Fig. 17 - Typical Recovery Current vs. dif/dt
560 480 400 320 240 IF = 30A V R = 85V TJ = 25C TJ = 125C
20
IRR (A)
15
10
5
160 80 0 200 400 600 800 1000 0 200 400 600 800 1000 diF /dt (A/s) diF /dt (A/s)
0
Fig. 18 - Typical Recovery Current vs. dif/dt
560 480 400
QRR (A)
Fig. 19 - Typical Stored Charge vs. dif/dt
IF = 45A V R = 85V TJ = 25C TJ = 125C
320 240 160 80 0 200 400 600 800 1000 diF /dt (A/s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
www.irf.com
IRFB4110PBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 21a. Unclamped Inductive Test Circuit
LD VDS
Fig 21b. Unclamped Inductive Waveforms
+
VDD D.U.T VGS Pulse Width < 1s Duty Factor < 0.1%
90%
VDS
10%
VGS
td(on) tr td(off) tf
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
Id Vds Vgs
L
0
DUT 1K
VCC
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
www.irf.com
Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
7
IRFB4110PBF
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
@Y6HQG@) UCDTADTA6IADSA A GPUA8P9@A &'( 6TT@H7G@9APIAXXA (A ((& DIAUC@A6TT@H7GAGDI@AA8A
Note: "P" in assembly line position indicates "Lead-Free"
DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G GPUA8P9@
Q6SUAIVH7@S 96U@A8P9@ @6SA&A2A ((& X@@FA ( GDI@A8
TO-220AB packages are not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
8
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 11/05
www.irf.com

▲Up To Search▲

Price & Availability of IRFB4110PBF

	To Download IRFB4110PBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .